In the development of so-called ASICs (Application-Specific Integrated Circuits), it is normally necessary to compare different version or optimization statuses of the circuit design with one another. Computer-aided methods, which compare a circuit with a reference circuit in respect of their functional equivalence, are known for this purpose. In this case, the circuit and the reference circuit are typically described by a circuit description language appropriate for computer-aided circuit design.
Such an equivalence comparison of circuits is performed particularly when it is to be checked whether a later version of the circuit design corresponds with an earlier version or the original version of the circuit design. In this way, it is possible to ensure that the circuit produced according to the final circuit design also has the functionality provided for according to the original circuit design.
If, on the other hand, a functional deviation between the circuit and the reference circuit is ascertained upon such an equivalence comparison of a circuit and a reference circuit, it is necessary to find and locate this functional deviation in the circuit design, in order that an appropriate correction can be made.
Known in this connection is the practice of locating the fault by means of a fault model. Such a fault model is normally based on a certain assumption concerning the nature of the fault (e.g., non-connected circuit networks or function blocks, additional inverters, etc.). Also known is the practice of using simulations to make probability statements concerning the fault site. A further approach is based on the ascertainment of internal equivalences of circuits. This means that individual circuit regions are in each case checked in pairs in respect of their equivalence. For this, however, it is first necessary to create possible pairings for such internal equivalences, an operation which can be performed, for example, on the basis of names used in the circuit description.
The previously described approaches for locating circuit deviations have problems, however, in that they require a large amount of effort and that, in some cases, it is not possible to state exactly the site of the deviation.